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| 1 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 typical application features applications description 14-bit, 65msps/40msps/ 25msps low power octal adcs ltm9008-14, 65msps, 2- tone fft , f in = 70mhz and 75mhz the lt m ? 9008-14/ ltm9007-14/ltm9006-14 are 8-chan - nel, simultaneous sampling 14-bit a / d converters designed for digitizing high frequency, wide dynamic range signals. ac performance includes 73db snr and 90db spurious free dynamic range (sfdr). low power consumption per channel reduces heat in high channel count applications. integrated bypass capacitance and flowthrough pinout reduces overall board space requirements. dc specs include 1lsb inl (typ), 0.3lsb dnl (typ) and no missing codes over temperature. the transition noise is a low 1.2lsb rms . the digital outputs are serial lvds to minimize the num- ber of data lines. each channel outputs two bits at a time (2-lane mode). at lower sampling rates there is a one bit per channel option (1-lane mode). the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds , ttl , or cmos inputs. an internal clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. n 8-channel simultaneous sampling adc n 73db snr n 90db sfdr n low power: 88mw/59mw/46mw per channel n single 1.8v supply n serial lvds outputs: 1 or 2 bits per channel n selectable input ranges: 1v p-p to 2v p-p n 800 mhz full power bandwidth s/h n shutdown and nap modes n serial spi port for configuration n internal bypass capacitance, no external components n 140- pin (11.25mm 9mm) bga package n communications n cellular base stations n software defined radios n portable medical imaging n multichannel data acquisition n nondestructive testing l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. data serializer encode input serialized lvds outputs 1.8v v dd 1.8v ov dd out1a out1b out2a out2b out8a out8b data clock out frame gnd gnd 90067814 ta01 s/h channel 1 analog input 14-bit adc core s/h channel 2 analog input 14-bit adc core s/h channel 8 analog input 14-bit adc core pll ? ? ? ? ? ? ? ? ? ? ? ? frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 90067814 ta01b
ltm 9008-14/ ltm 9007-14/ ltm 9006-14 2 90067814f absolute maximum ratings (notes 1, 2) pin configuration order information lead free finish tray part marking* package description temperature range ltm9008cy-14#pbf ltm9008cy-14#pbf ltm9008y14 140-lead (11.25mm 9mm 2.72mm) bga 0c to 70c ltm9008iy-14#pbf ltm9008iy-14#pbf ltm9008y14 140-lead (11.25mm 9mm 2.72mm) bga C40c to 85c ltm9007cy-14#pbf ltm9007cy-14#pbf ltm9007y14 140-lead (11.25mm 9mm 2.72mm) bga 0c to 70c ltm9007iy-14#pbf ltm9007iy-14#pbf ltm9007y14 140-lead (11.25mm 9mm 2.72mm) bga C40c to 85c ltm9006cy-14#pbf ltm9006cy-14#pbf ltm9006y14 140-lead (11.25mm 9mm 2.72mm) bga 0c to 70c ltm9006iy-14#pbf ltm9006iy-14#pbf ltm9006y14 140-lead (11.25mm 9mm 2.72mm) bga C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ supply voltages v dd , ov dd ................................................ C0.3 v to 2 v analog input voltage ( a in + , a in C , par / ser , sense ) ( note 3) .......... C0.3 v to ( v dd + 0.2 v ) digital input voltage ( enc + , enc C , cs , sdi , sck ) ( note 4) .................................... C0.3 v to 3.9 v sdo ( note 4) ............................................. C0.3 v to 3.9 v digital output voltage ................ C0.3 v to ( ov dd + 0.3 v ) operating temperature range ltm 9008 c , ltm 9007 c , ltm 9006 c ......... 0 c to 70 c ltm 9008 i , ltm 9007 i , ltm 9006 i ........ C40 c to 85 c storage temperature range .................. C55 c to 125 c 1 p c d e f g h j k l m n a b 1098765432 bga package 140-lead (11.25mm 9.00mm 2.72mm) top view t jmax = 150c, ja = 30c/w, jc = 25c/w, jb = 15c/w, jcbottom = 12c/w 3 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 converter characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions ltm9008-14 ltm9007-14 ltm9006-14 units min typ max min typ max min typ max resolution (no missing codes) l 14 14 14 bits integral linearity error differential analog input (note 6) l C4.1 1.2 4.1 C2.75 1 2.75 C2.75 1 2.75 lsb differential linearity error differential analog input l C0.9 0.3 0.9 C0.8 0.3 0.8 C0.8 0.3 0.8 lsb offset error (note 7) l C12 3 12 C12 3 12 C12 3 12 mv gain error internal reference external reference l C2.5 C1.3 C1.3 0.5 C2.5 C1.3 C1.3 0.5 C2.6 C1.3 C1.3 0.5 %fs %fs offset drift 20 20 20 v/c full-scale drift internal reference external reference 35 25 35 25 35 25 ppm/c ppm/c gain matching external reference 0.2 0.2 0.2 %fs offset matching 3 3 3 mv transition noise external reference 1.2 1.2 1.2 lsb rms analog input the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.7v < v dd < 1.9v l 1 to 2 v p-p v in(cm) analog input common mode ( a in + + a in C )/2 differential analog input (note 8) l v cm C 100mv v cm v cm + 100mv v v sense external voltage reference applied to sense external reference mode l 0.625 1.250 1.300 v i incm analog input common mode current per pin, 65msps per pin, 40msps per pin, 25msps 81 50 31 a a a i in1 analog input leakage current 0 < a in + , a in C < v dd , no encode l C1 1 a i in2 par /ser input leakage current 0 < par /ser < v dd l C3 3 a i in3 sense input leakage current 0.625 < sense < 1.3v l C6 6 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter 0.15 ps rms cmrr analog input common mode rejection ratio 80 db bw-3b full-power bandwidth figure 6 test circuit 800 mhz ltm 9008-14/ ltm 9007-14/ ltm 9006-14 4 90067814f dynamic accuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions ltm9008-14 ltm9007-14 ltm9006-14 units min typ max min typ max min typ max snr signal-to-noise ratio 5mhz input 30mhz input 70mhz input 140mhz input l 71.8 73.7 73.7 73.5 73 69.6 73.5 73.4 73.4 72.8 69.6 72.9 72.9 72.8 72.3 dbfs dbfs dbfs dbfs sfdr spurious free dynamic range 2nd or 3rd harmonic 5mhz input 30mhz input 70mhz input 140mhz input l 74 90 90 89 84 76.8 90 90 89 84 76.8 90 90 89 84 dbfs dbfs dbfs dbfs spurious free dynamic range 4th harmonic or higher 5mhz input 30mhz input 70mhz input 140mhz input l 84 90 90 90 90 84 90 90 90 90 84 90 90 90 90 dbfs dbfs dbfs dbfs s/(n+d) signal-to-noise plus distortion ratio 5mhz input 30mhz input 70mhz input 140mhz input l 71 73.6 73.5 73.2 72.5 69.5 73.3 73.2 73.1 72.3 69.5 72.8 72.7 72.5 71.9 dbfs dbfs dbfs dbfs crosstalk, near channel 10mhz input (note 12) C90 C90 C90 dbc crosstalk, far channel 10mhz input (note 12) C105 C105 C105 dbc internal reference characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) parameter conditions min typ max units v cm output voltage i out = 0 0.5 ? v dd C 25mv 0.5 ? v dd 0.5 ? v dd + 25mv v v cm output temperature drift 25 ppm/c v cm output resistance C600a < i out < 1ma 4 v ref output voltage i out = 0 1.225 1.250 1.275 v v ref output temperature drift 25 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v 5 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 digital inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) differential encode mode (enc C not tied to gnd) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.6 v v v in input voltage range enc + , enc C to gnd l 0.2 3.6 v r in input resistance (see figure 10) 10 k c in input capacitance 3.5 pf single-ended encode mode (enc C tied to gnd) v ih high level input voltage v dd = 1.8v 1.26 v v il low level input voltage v dd = 1.8v 0.54 v v in input voltage range enc + to gnd 0 to 3.6 v r in input resistance (see figure 11) 30 k c in input capacitance 3.5 pf digital inputs (cs, sdi, sck in serial or parallel programming mode. sdo in parallel programming mode) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance 3 pf sdo output (serial programming mode. open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance 3 pf digital d ata outputs v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 247 125 350 175 454 250 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 1.125 1.125 1.250 1.250 1.375 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100 ltm 9008-14/ ltm 9007-14/ ltm 9006-14 6 90067814f power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) symbol parameter conditions ltm9008-14 ltm9007-14 ltm9006-14 units min typ max min typ max min typ max v dd analog supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v i vdd analog supply current sine wave input l 357 400 232 275 175 250 ma i ovdd digital supply current 1-lane mode, 1.75ma mode 1-lane mode, 3.5ma mode 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode l l 32 60 50 94 58 104 32 58 48 92 54 102 30 56 48 90 54 100 ma ma ma ma p diss power dissipation 1-lane mode, 1.75ma mode 1-lane mode, 3.5ma mode 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode l l 700 751 733 812 824 907 475 522 504 583 592 679 369 416 401 477 547 630 mw mw mw mw p sleep sleep mode power 2 2 2 mw p nap nap mode power 170 170 170 mw p diffclk power decrease with single- ended encode mode enabled (no decrease for sleep mode) 40 40 40 mw timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions ltm9008-14 ltm9007-14 ltm9006-14 units min typ max min typ max min typ max f s sampling frequency (notes 10,11) l 5 65 5 40 5 25 mhz t encl enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 7.3 2 7.69 7.69 100 100 11.88 2 12.5 12.5 100 100 19 2 20 20 100 100 ns ns t ench enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 7.3 2 7.69 7.69 100 100 11.88 2 12.5 12.5 100 100 19 2 20 20 100 100 ns ns t ap sample-and-hold acquisition delay time 0 0 0 ns symbol parameter conditions min typ max units digital data outputs (r term = 100 differential, c l = 2pf to gnd on each output) t ser serial data bit period 2-lanes, 16-bit serialization 2-lanes, 14-bit serialization 2-lanes, 12-bit serialization 1-lane, 16-bit serialization 1-lane, 14-bit serialization 1-lane, 12-bit serialization 1/(8 ? f s ) 1/(7 ? f s ) 1/(6 ? f s ) 1/(16 ? f s ) 1/(14 ? f s ) 1/(12 ? f s ) s s s s s s t frame fr to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser s t data data to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser s t pd propagation delay (note 8) l 0.7n + 2 ? t ser 1.1n + 2 ? t ser 1.5n + 2 ? t ser s t r output rise time data, dco, fr, 20% to 80% 0.17 ns t f output fall time data, dco, fr, 20% to 80% 0.17 ns dco cycle-cycle jitter t ser = 1ns 60 ps p-p pipeline latency 6 cycles 7 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 symbol parameter conditions min typ max units spi port timing (note 8) t sck sck period write mode read back mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck setup time l 5 ns t h sck to cs setup time l 5 ns t ds sdi setup time l 5 ns t dh sdi hold time l 5 ns t do sck falling to sdo valid read back mode, c sdo = 20pf, r pullup = 2k l 125 ns timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 65mhz (ltm9008), 40mhz (ltm9007), or 25mhz (ltm9006), 2-lane output mode, differential enc + / enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: v dd = ov dd = 1.8v, f sample = 65mhz (ltm9008), 40mhz (ltm9007), or 25mhz ( ltm9006), 2-lane output mode, differential enc + /enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. the supply current and power dissipation specifications are totals for the entire device, not per channel. note 10: recommended operating conditions. note 11: the maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. the maximum serial data rate is 1000mbps so t ser must be greater than or equal to 1ns. note 12: near-channel crosstalk refers to ch. 1 to ch.2, and ch.7 to ch.8. far- channel crosstalk refers to ch.1 to ch.7, ch.1 to ch.8, ch.2 to ch.7, and ch.2 to ch.8. ltm 9008-14/ ltm 9007-14/ ltm 9006-14 8 90067814f 2-lane output mode, 14-bit serialization timing diagrams 2-lane output mode, 16-bit serialization* analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 *see the digital outputs section sample n-5 sample n-4 n+1 n 90067814 td01 d5 d3 d1 0 d13 d11 d9 d7 d5 d3 d1 0 d13 d11 d9 out#a ? out#a + fr ? fr + d4 d2 d0 0 d12 d10 d8 d6 d4 d2 d0 0 d12 d10 d8 out#b ? out#b + analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 sample n-5 sample n-4 sample n-3 n+1 n+2 n 90067814 td02 d7 d5 d3 d1 d13 d11 d9 d7 d5 d3 d1 d13 d11 d9 d7 d5 d3 d1 d13 d11 d9 out#a ? out#a + fr ? fr + d6 d4 d2 d0 d12 d10 d8 d6 d4 d2 d0 d12 d10 d8 d6 d4 d2 d0 d12 d10 d8 out#b ? out#b + note that in this mode fr + /fr ? has two times the period of enc + /enc ? 9 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 timing diagrams 2-lane output mode, 12-bit serialization 1-lane output mode, 16-bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n 90067814 td03 d9 d7 d5 d3 d13 d11 d9 d7 d5 d3 d13 d11 d9 out#a ? out#a + fr + fr ? d8 d6 d4 d2 d12 d10 d8 d6 d4 d2 d12 d10 d8 out#b ? out#b + analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 90067814 td04 d1 d0 0 0 d13 d12 d11 d10 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 d13 out#a ? out#a + fr ? fr + out#b + , out#b ? are disabled 1- lane output mode, 14-bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 90067814 td06 d3 d2 d1 d0 d13 d12 d11 d10 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 out#a ? out#a + fr ? fr + out#b + , out#b ? are disabled ltm 9008-14/ ltm 9007-14/ ltm 9006-14 10 90067814f timing diagrams 1-lane output mode, 12-bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 90067814 td07 d5 d4 d3 d2 d13 d12 d11 d10 d12 d11 d9 d8 d7 d6 d5 d4 d3 d2 d13 out#a ? out#a + fr ? fr + out#b + , out#b ? are disabled a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 90067814 td08 cs sck sdi r/w sdo high impedance 11 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 typical performance characteristics ltm9008-14: integral nonlinearity (inl) vs output code ltm9008-14: differential nonlinearity (dnl) vs output code ltm9008-14: 64k point fft , f in = 5mhz, C1dbfs, sense = v dd ltm9008-14: 64k point fft , f in = 30mhz, C1dbfs, sense = v dd ltm9008-14: 64k point fft , f in = 70mhz, C1dbfs, sense = v dd ltm9008-14: 64k point 2- tone fft , f in = 28.5mhz and f in = 31.5mhz, C7dbfs per tone, sense = v dd ltm9008-14: shorted input histogram output code 0 inl error (lsb) 0 1.0 16384 90067814 g01 ?1.0 ?2.0 4096 8192 12288 2.0 ?0.5 0.5 ?1.5 1.5 output code 0 ?0.5 dnl error (lsb) ?0.4 ?0.2 ?0.1 0 0.5 0.2 4096 8192 90067814 g02 ?0.3 0.3 0.4 0.1 12288 16384 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 90067814 g03 ?100 ?110 ?40 ?60 ?90 ?30 ?120 ?50 ?70 5 15 30 35 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 90067814 g04 ?100 ?110 ?40 ?60 ?90 ?30 ?120 ?50 ?70 5 15 30 35 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 90067814 g05 ?100 ?110 ?40 ?60 ?90 ?30 ?120 ?50 ?70 5 15 30 35 frequency (mhz) 0 amplitude (dbfs) ?80 ?20 ?10 0 10 20 25 90067814 g06 ?100 ?110 ?40 ?60 ?90 ?30 ?120 ?50 ?70 5 15 30 35 output code 8197 1000 0 3000 2000 count 4000 5000 6000 8199 8201 8203 8205 90067814 g07 ltm 9008-14/ ltm 9007-14/ ltm 9006-14 12 90067814f typical performance characteristics ltm9008-14: snr vs input frequency, C1dbfs, 2v range, 65msps ltm9008-14: sfdr vs input level, f in = 70mhz, 2v range, 65msps ltm9008-14: i vdd vs sample rate, 5mhz sine wave input, C1dbfs ltm9008-14: sfdr vs input frequency, C1dbfs, 2v range, 65msps i ovdd vs sample rate, 5mhz sine wave input, C1dbfs ltm9008-14: snr vs sense, f in = 5mhz, C1dbfs ltm9008-14: snr vs input level, f in = 70 mhz, 2v range, 65msps input frequency (mhz) 0 72 71 70 69 68 67 66 74 73 snr (dbfs) 50 100 150 200 250 300 350 90067814 g08 input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 90067814 g09 input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 90067814 g11 dbfs dbc input level (dbfs) 60 50 40 30 20 10 0 80 70 snr (dbc and dbfs) ?60 ?50 ?40 ?30 ?20 ?10 0 90067814 g11 dbc dbfs sample rate (msps) 320 310 300 290 280 270 260 250 240 230 220 i vdd (ma) 0 10 20 30 40 50 60 90067814 g12 sense pin (v) 0.6 72 69 70 71 68 67 73 74 75 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 90067814 g14 sample rate (msps) 50 40 30 20 10 0 i ovdd (ma) 0 20 40 60 90067814 g13 1-lane, 1.75ma 2-lane, 3.5ma 2-lane, 1.75ma 1-lane, 3.5ma 13 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 typical performance characteristics ltm9007-14: integral nonlinearity (inl) vs output code ltm9007-14: differential nonlinearity (dnl) vs output code ltm9007-14: 64k point fft , f in = 5mhz, C1dbfs, sense = v dd ltm9007-14: shorted input histogram ltm9007-14: 64k point fft , f in = 70mhz, C1dbfs, sense = v dd ltm9007-14: 64k point 2- tone fft , f in = 28.5mhz and f in = 31.5mhz, C7dbfs per tone, sense = v dd ltm9007-14: 64k point fft , f in = 30mhz, C1dbfs, sense = v dd output code 0 inl error (lsb) 0 1.0 16384 90067814 g15 ?1.0 ?2.0 4096 8192 12288 2.0 ?0.5 0.5 ?1.5 1.5 output code 0 ?0.5 dnl error (lsb) ?0.4 ?0.2 ?0.1 0 0.5 0.2 4096 8192 90067814 g16 ?0.3 0.3 0.4 0.1 12288 16384 frequency (mhz) 0 amplitude (dbfs) ?60 ?30 ?20 20 90067814 g17 ?70 ?80 ?120 5 10 15 ?100 0 ?10 ?40 ?50 ?90 ?110 frequency (mhz) 0 amplitude (dbfs) ?60 ?30 ?20 20 90067814 g18 ?70 ?80 ?120 5 10 15 ?100 0 ?10 ?40 ?50 ?90 ?110 frequency (mhz) 0 amplitude (dbfs) ?60 ?30 ?20 20 90067814 g19 ?70 ?80 ?120 5 10 15 ?100 0 ?10 ?40 ?50 ?90 ?110 frequency (mhz) 0 amplitude (dbfs) ?60 ?30 ?20 20 90067814 g20 ?70 ?80 ?120 2 8 14 4 10 16 6 12 18 ?100 0 ?10 ?40 ?50 ?90 ?110 output code 8198 1000 0 3000 2000 count 4000 5000 6000 8200 8202 8204 8206 90067814 g21 ltm 9008-14/ ltm 9007-14/ ltm 9006-14 14 90067814f ltm9007-14: i vdd vs sample rate, 5mhz sine wave input, C1dbfs ltm9007-14: sfdr vs input level, f in = 70mhz, 2v range, 40msps typical performance characteristics ltm9007-14: snr vs input frequency, C1dbfs, 2v range, 40msps ltm9007-14: sfdr vs input frequency, C1dbfs, 2v range, 40msps ltm9007-14: snr vs sense, f in = 5mhz, C1dbfs input frequency (mhz) 0 72 71 70 69 68 67 66 74 73 snr (dbfs) 50 100 150 200 250 300 350 90067814 g22 input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 90067814 g23 input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 90067814 g24 dbfs dbc sample rate (msps) 200 190 180 170 160 150 140 i vdd (ma) 0 10 20 30 40 90067814 g25 sense pin (v) 0.6 71 68 69 70 67 66 72 73 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 90067814 g26 15 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 typical performance characteristics ltm9006-14: 64k point 2- tone fft , f in = 28.5mhz and 31.5mhz, C7dbfs per tone, sense = v dd ltm9006-14: shorted input histogram ltm9006-14: 64k point fft , f in = 30mhz, C1dbfs, sense = v dd ltm9006-14: 64k point fft , f in = 70mhz, C1dbfs, sense = v dd ltm9006-14: integral nonlinearity (inl) vs output code ltm9006-14: differential nonlinearity (dnl) vs output code ltm9006-14: 64k point fft , f in = 5mhz, C1dbfs, sense = v dd output code 0 inl error (lsb) 0 1.0 16384 90067814 g27 ?1.0 ?2.0 4096 8192 12288 2.0 ?0.5 0.5 ?1.5 1.5 output code 0 ?0.5 dnl error (lsb) ?0.4 ?0.2 ?0.1 0 0.5 0.2 4096 8192 90067814 g28 ?0.3 0.3 0.4 0.1 12288 16384 frequency (mhz) 0 amplitude (dbfs) ?60 ?30 ?20 14 90067814 g29 ?70 ?80 ?120 2 8 4 10 6 12 ?100 0 ?10 ?40 ?50 ?90 ?110 frequency (mhz) 0 amplitude (dbfs) ?60 ?30 ?20 14 90067814 g30 ?70 ?80 ?120 2 8 4 10 6 12 ?100 0 ?10 ?40 ?50 ?90 ?110 frequency (mhz) 0 amplitude (dbfs) ?60 ?30 ?20 14 90067814 g31 ?70 ?80 ?120 2 8 4 10 6 12 ?100 0 ?10 ?40 ?50 ?90 ?110 frequency (mhz) 0 amplitude (dbfs) ?60 ?30 ?20 14 90067814 g32 ?70 ?80 ?120 2 8 4 10 6 12 ?100 0 ?10 ?40 ?50 ?90 ?110 output code 8198 1000 0 3000 2000 count 4000 5000 6000 8200 8202 8204 8206 90067814 g33 ltm 9008-14/ ltm 9007-14/ ltm 9006-14 16 90067814f typical performance characteristics ltm9006-14: i vdd vs sample rate, 5mhz sine wave input, C1dbfs dco cycle-cycle jitter vs serial data rate ltm9006-14: snr vs sense, f in = 5mhz, C1dbfs ltm9006-14: sfdr vs input level, f in = 70mhz, 2v range, 25msps ltm9006-14: sfdr vs input frequency, C1dbfs, 2v range, 25msps ltm9006-14: snr vs input frequency, C1dbfs, 2v range, 25msps input frequency (mhz) 0 72 71 70 69 68 67 66 74 73 snr (dbfs) 50 100 150 200 250 300 350 90067814 g34 input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 90067814 g35 input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 90067814 g36 dbfs dbc sample rate (msps) 160 150 140 130 120 i vdd (ma) 0 5 10 15 2520 90067814 g37 sense pin (v) 0.6 71 68 69 70 67 66 72 73 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 90067814 g38 serial data rate (mbps) 350 300 250 200 150 100 50 0 peak-to-peak jitter (ps) 0 200 400 600 800 1000 90067814 g39 17 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 pin functions a in1 + (b2): channel 1 positive differential analog input. a in1 C (b1): channel 1 negative differential analog input. v cm12 (b3): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channels 1 and 2. v cm is internally bypassed to ground with a 0.1f ceramic capacitor. no external capacitance is required. a in2 + (c2): channel 2 positive differential analog input. a in2 C (c1): channel 2 negative differential analog input. a in3 + (e2): channel 3 positive differential analog input. a in3 C (e1): channel 3 negative differential analog input. v cm34 (f3): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channels 3 and 4. v cm is internally bypassed to ground with a 0.1f ceramic capacitor. no external capacitance is required. a in4 + (g2): channel 4 positive differential analog input. a in4 C (g1): channel 4 negative differential analog input. a in5 + (h1): channel 5 positive differential analog input. a in5 C (h2): channel 5 negative differential analog input. v cm56 (j3): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channels 5 and 6. v cm is internally bypassed to ground with a 0.1f ceramic capacitor. no external capacitance is required. a in6 + (k1): channel 6 positive differential analog input. a in6 C (k2): channel 6 negative differential analog input. a in7 + (m1): channel 7 positive differential analog input. a in7 C ( m2): channel 7 negative differential analog input. v cm 78 (n3): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channels 7 and 8. v cm is internally bypassed to ground with a 0.1f ceramic capacitor. no external capacitance is required. a in8 + (n1): channel 8 positive differential analog input. a in8 C (n2): channel 8 negative differential analog input v dd (d3, d4, e3, e 4, k3, k4, l3, l4): 1.8v analog power supply. v dd is internally bypassed to ground with 0.1f ceramic capacitors. enc + (p5): encode input. conversion starts on the rising edge. enc C (p6): encode complement input. conversion starts on the falling edge. csa (l5): in serial programming mode, ( par /ser = 0 v), csa is the serial interface chip select input for registers controlling channels 1, 4, 5 and 8. when cs is low, sck is enabled for shifting data on sdi into the mode control registers . in parallel programming mode ( par / ser = v dd ), cs selects 2-lane or 1-lane output mode. cs can be driven with 1.8v to 3.3v logic. csb (m5): in serial programming mode, ( par /ser = 0 v), csb is the serial interface chip select input for registers controlling channels 2, 3, 6 and 7. when cs is low, sck is enabled for shifting data on sdi into the mode control registers . in parallel programming mode ( par / ser = v dd ), cs selects 2-lane or 1-lane output mode. cs can be driven with 1.8v to 3.3v logic. sck (l6): in serial programming mode, ( par /ser = 0v), sck is the serial interface clock input. in parallel programming mode ( par /ser = v dd ), sck selects 3.5ma or 1.75ma lvds output currents. sck can be driven with 1.8v to 3.3v logic. sdi (m6): in serial programming mode , ( par /ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in parallel programming mode ( par /ser = v dd ), sdi can be used to power down the part. sdi can be driven with 1.8v to 3.3v logic. gnd (see pin configuration table ): adc power ground. use multiple vias close to pins. ltm 9008-14/ ltm 9007-14/ ltm 9006-14 18 90067814f pin functions ov dd ( g9, g10): output driver supply. ov dd is internally bypassed to ground with a 0.1f ceramic capacitor. sdoa ( e 6): in serial programming mode , ( par / ser = 0 v), sdoa is the optional serial interface data output for registers controlling channels 1, 4, 5 and 8. data on sdo is read back from the mode control registers and can be latched on the falling edge of sck. sdo is an open -drain n-channel mosfet output that requires an external 2k pull-up resistor from 1.8v to 3.3v. if read back from the mode control registers is not needed, the pull-up resis- tor is not necessary and sdo can be left unconnected. in parallel programming mode ( par /ser = v dd ), sdoa is an input that enables internal 100 termination resistors on the digital outputs of channels 1, 4, 5 and 8. when used as an input, sdo can be driven with 1.8v to 3.3v logic through a 1k series resistor. sdob (d6): serial data output pin for channels 2, 3, 6 and 7. see description for sdoa. par / ser ( a 7): programming mode selection pin . connect to ground to enable the serial programming mode. csa, csb, sck, sdi, sdoa and sdob become a serial interface that control the a/d operating modes. connect to v dd to enable parallel programming mode where csa, csb, sck, sdi, sdoa and sdob become parallel logic inputs that control a reduced set of the a/d operating modes. par / ser should be connected directly to ground or the v dd of the part and not be driven by a logic signal. v ref (b6): reference voltage output. v ref is internally bypassed to ground with a 1f ceramic capacitor, nomi- nally 1.25v. sense (c5): reference programming pin. connecting sense to v dd selects the internal reference and a 1v input range. connecting sense to ground selects the internal reference and a 0.5v input range. an external reference between 0.625v and 1.3v applied to sense selects an input range of 0.8 ? v sense . sense is internally bypassed to ground with a 0.1f ceramic capacitor. lvds outputs all pins in this section are differential lvds outputs. the output current level is programmable. there is an optional internal 100? termination resistor between the pins of each lvds output pair. out 1 a C / out 1 a + , out 1 b C / out 1 b + ( e 7/ e 8, c 8/ d 8): serial data outputs for channel 1. in 1-lane output mode only out1a C /out1a + are used. out 2 a C / out 2 a + , out 2 b C / out 2 b + ( b 8/ a 8, d 7/ c 7): serial data outputs for channel 2. in 1-lane output mode only out2a C /out2a + are used. out3a C /out3a + , out3b C /out3b + (d10/d9, e10/e9): serial data outputs for channel 3. in 1-lane output mode only out3a C /out3a + are used. out4 a C / out4 a + , out4 b C / out4 b + ( c 9/c 10, f 7/f 8): serial data outputs for channel 4. in 1-lane output mode only out4a C /out4a + are used. out5 a C / out5 a + , out5 b C / out5 b + ( j 8/j 7, k 8/k 7): serial data outputs for channel 5. in 1-lane output mode only out5a C /out5a + are used. out 6 a C / out 6 a + , out 6 b C / out 6 b + ( k 9/ k 10, l 9/ l 10): serial data outputs for channel 6. in 1-lane output mode only out6a C /out6a + are used. out7 a C / out7 a + , out7 b C / out7 b + ( m 7/l 7, p 8/n 8): serial data outputs for channel 7. in 1-lane output mode only out7a C /out7a + are used. out8a C /out8a + , out8b C /out8b + (l8/m8, m10/m9): serial data outputs for channel 8. in 1-lane output mode only out8a C /out8a + are used. fra C /fra + (h7/h8): frame start outputs for channels 1, 4, 5 and 8. frb C /frb + (j9/j10): frame start outputs for channels 2, 3, 6 and 7. dcoa C /dcoa + (g8/g7): data clock outputs for channels 1, 4, 5 and 8. dcob C /dcob + (f10, f9): data clock outputs for chan- nels 2, 3, 6 and 7. 19 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 1 2 3 4 5 6 7 8 9 10 a gnd gnd gnd gnd gnd gnd par /ser o2a + gnd gnd b a in1 C a in1 + v cm12 gnd gnd v ref gnd o2a C gnd gnd c a in2 C a in2 + gnd gnd sense gnd o2b + o1b C o4a C o4a + d gnd gnd v dd v dd gnd sdob o2b C o1b + o3a + o3a C e a in3 C a in3 + v dd v dd gnd sdoa o1a C o1a + o3b + o3b C f gnd gnd v cm34 gnd gnd gnd o4b C o4b + dcob + dcob C g a in4 C a in4 + gnd gnd gnd gnd dcoa + dcoa C ov dd ov dd h a in5 + a in5 C gnd gnd gnd gnd fra C fra + gnd gnd j gnd gnd v cm56 gnd gnd gnd o5a + o5a C frb C frb + k a in6 + a in6 C v dd v dd gnd gnd o5b + o5b C o6a C o6a + l gnd gnd v dd v dd csa sck o7a + o8a C o6 b C o6b + m a in7 + a in7 C gnd gnd csb sdi o7a C o8a + o8b + o8b C n a in8 + a in8 C v cm78 gnd gnd gnd gnd o7b + gnd gnd p gnd gnd gnd gnd clk + clk C gnd o7b C gnd gnd top view of bga package (looking through component). pin configuration table ltm 9008-14/ ltm 9007-14/ ltm 9006-14 20 90067814f functional block diagram figure 1. functional block diagram diff ref amp ref buffer refh refl range select 1.25v reference gnd v dd /2 90067814 f01 sense v ref mode control registers ov dd = 1.8v v dd = 1.8v out1a + out1a ? out1b + out1b ? s/h ch 1 analog input 14-bit adc core out2a + out2a ? out2b + out2b ? s/h ch 2 analog input 14-bit adc core out3a + out3a ? out3b + out3b ? s/h ch 3 analog input 14-bit adc core out4a + out4a ? out4b + out4b ? s/h ch 4 analog input 14-bit adc core out5a + out5a ? out5b + out5b ? s/h ch 5 analog input 14-bit adc core out6a + out6a ? out6b + out6b ? s/h ch 6 analog input 14-bit adc core out7a + out7a ? out7b + out7b ? s/h ch 7 analog input 14-bit adc core out8a + out8a ? out8b + out8b ? s/h ch 8 analog input 14-bit adc core dcoa dcob fra frb enc + enc ? sdoa sdob sdi sck csa csb par/ ser vcm12 vcm34 vcm56 vcm78 pll data serializer 21 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 applications information converter operation the ltm 9008 -14/ ltm 9007 -14/ ltm 9006 -14 are low power, 8-channel, 14-bit, 65msps/40msps/25msps a/d converters that are powered by a single 1.8v supply. the analog inputs should be driven differentially. the encode input can be driven differentially for optimal jitter perfor - mance , or single - ended for lower power consumption . the digital outputs are serial lvds to minimize the number of data lines. each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). many additional features can be chosen by programming the mode control registers through a serial spi port. analog input the analog inputs are differential cmos sample-and-hold circuits ( figure 2). the inputs should be driven differentially around a common mode voltage set by the appropriate v cm output pins, which are nominally v dd /2. for the 2v input range, the inputs should swing from v cm C 0.5v to v cm + 0.5 v. there should be 180 phase difference between the inputs. the eight channels are simultaneously sampled by a shared encode circuit (figure 2). input drive circuits input filtering if possible, there should be an rc low pass filter right at the analog inputs. this lowpass filter isolates the drive circuitry from the a / d sample- and- hold switching , and also limits wideband noise from the drive circuitry . figure 3 shows an example of an input rc filter. the rc component values should be chosen based on the applications input frequency. transformer coupled circuits figure 3 shows the analog input being driven by an rf transformer with a center-tapped secondary . the center tap is biased with v cm , setting the a/d input at its opti- mal dc level. at higher input frequencies a transmission line balun transformer (figures 4 to 6) has better balance, resulting in lower a/d distortion. figure 2. equivalent input circuit. only one of the eight analog channels is shown figure 3. analog input circuit using a transformer. recommended for input frequencies from 5mhz to 70mhz c sample 3.5pf r on 25 r on 25 v dd v dd ltm9008-14 a in + 90067814 f02 c sample 3.5pf v dd a in ? enc ? enc + 1.2v 10k 1.2v 10k c parasitic 1.8pf c parasitic 1.8pf 10 10 25 25 25 25 50 0.1f a in + a in ? 12pf 0.1f v cm ltm9008-14 analog input 0.1f t1 1:1 t1: ma/com mabaes0060 resistors, capacitors are 0402 package size 90067814 f03 ltm 9008-14/ ltm 9007-14/ ltm 9006-14 22 90067814f applications information amplifier circuits figure 7 shows the analog input being driven by a high speed differential amplifier. the output of the amplifier is ac-coupled to the a/d so the amplifiers output common mode voltage can be optimally set to minimize distortion. see back page for a dc-coupled example. figure 4. recommended front end circuit for input frequencies from 70mhz to 170mhz at very high frequencies an rf gain block will often have lower distortion than a differential amplifier. if the gain block is single-ended, then a transformer circuit (figures ?4 to 6) should convert the signal to differential before driv- ing the a/d. figure 5. recommended front end circuit for input frequencies from 170mhz to 300mhz figure 6. recommended front end circuit for input frequencies above 300mhz figure 7. front end circuit using a high speed differential amplifier 25 25 50 0.1f a in + a in ? 4.7pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: ma/com mabaes0060 resistors, capacitors are 0402 package size 90067814 f04 ltm9008-14 25 25 50 0.1f a in + a in ? 1.8pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1lb resistors, capacitors are 0402 package size 90067814 f05 ltm9008-14 25 25 50 0.1f 2.7nh 2.7nh a in + a in ? 0.1f v cm analog input 0.1f 0.1f t1 t1: ma/com etc1-1-13 resistors, capacitors are 0402 package size 90067814 f06 ltm9008-14 25 25 200 200 0.1f a in + a in ? 12pf 0.1f v cm ltm9008-14 90067814 f07 ? ? + + analog input high speed differential amplifier 0.1f 23 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 applications information figure 8. reference circuit figure 9. using an external 1.25v reference reference the ltm9008-14/ltm9007-14/ltm9006-14 has an inter - nal 1.25v voltage reference. for a 2v input range using the internal reference, connect sense to v dd . for a 1v input range using the internal reference, connect sense to ground. for a 2v input range with an external reference, apply a 1.25v reference voltage to sense (figure 9). the input range can be adjusted by applying a voltage to sense that is between 0.625v and 1.30v. the input range will then be 1.6 ? v sense . the reference is shared by all eight adc channels, so it is not possible to independently adjust the input range of individual channels. the v ref , sense, refh and refl pins are internally bypassed, as shown in figure 8. v ref 1.25v sense tie to v dd for 2v range; tie to gnd for 1v range; range = 1.6 ? v sense for 0.65v < v sense < 1.300v 0.1f 2.2f internal adc high reference buffer 90067814 f08 ltm9008-14 5 0.8x diff amp internal adc low reference 1.25v bandgap reference 0.625v range detect and control 1f 0.1f 0.1f 0.1f sense 1.25v external reference 1f 90067814 f09 ltm9008-14 ltm 9008-14/ ltm 9007-14/ ltm 9006-14 24 90067814f applications information encode input the signal quality of the encode inputs strongly affects the a/d noise performance . the encode inputs should be treated as analog signalsdo not route them next to digital traces on the circuit board. there are two modes of operation for the encode inputs: the differential encode mode (figure 10), and the single-ended encode mode (figure 11). the differential encode mode is recommended for sinu- soidal, pecl, or lvds encode inputs (figures 12 and 13). figure 13. pecl or lvds encode drive figure 12. sinusoidal encode drive figure 10. equivalent encode input circuit for differential encode mode figure 11. equivalent encode input circuit for single-ended encode mode the encode inputs are internally biased to 1.2v through 10k equivalent resistance. the encode inputs can be taken above v dd ( up to 3.6v), and the common mode range is from 1.1v to 1.6v. in the differential encode mode, enc C should stay at least 200mv above ground to avoid falsely triggering the single-ended encode mode. for good jitter performance enc + should have fast rise and fall times. the single - ended encode mode should be used with cmos encode inputs. to select this mode, enc C is connected to ground and enc + is driven with a square wave encode v dd ltm9008-14 90067814 f10 enc ? enc + 15k v dd differential comparator 30k 30k enc + enc ? 90067814 f11 0v 1.8v to 3.3v ltm9008-14 cmos logic buffer 50 100 0.1f 0.1f 0.1f t1 t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 ltm9008-14 90067814 f12 enc ? enc + enc + enc ? pecl or lvds clock 0.1f 0.1f 90067814 f13 ltm9008-14 25 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 applications information input. enc + can be taken above v dd ( up to 3.6v) so 1.8v to 3.3 v cmos logic levels can be used . the enc + threshold is 0.9v. for good jitter performance enc + should have fast rise and fall times. clock pll and duty cycle stabilizer the encode clock is multiplied by an internal phase-locked loop (pll) to generate the serial digital output data. if the encode signal changes frequency or is turned off, the pll requires 25s to lock onto the input clock. a clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. in the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. in the parallel programming mode the duty cycle stabilizer is always enabled. digital outputs the digital outputs of the ltm9008-14/ltm9007-14/ ltm9006-14 are serialized lvds signals. each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). the data can be serialized with 16, 14, or 12- bit serialization (see the timing diagrams section for details). note that with 12-bit serialization the two lsbs are not availablethis mode is included for compatibility with 12-bit versions of these parts. the output data should be latched on the rising and falling edges of the data clock out (dco). a data frame output (fr) can be used to determine when the data from a new conversion result begins. in the 2-lane, 14-bit serialization mode, the frequency of the fr output is halved. the maximum serial data rate for the data outputs is 1gbps, so the maximum sample rate of the adc will de- pend on the serialization mode as well as the speed grade of the adc (see table 1). the minimum sample rate for all serialization modes is 5msps. by default the outputs are standard lvds levels: 3.5ma output current and a 1.25v output common mode volt- age. an external 100? differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. table 1. maximum sampling frequency for all serialization modes. note that these limits are for the ltm9008-14. the sampling frequency for the slower speed grades cannot exceed 40mhz (ltm9007-14) or 25mhz (ltm9006-14) serialization mode maximum sampling frequency, f s (mhz) dco frequency fr frequency serial d ata rate 2-lane 16-bit serialization 65 4 ? f s f s 8 ? f s 2-lane 14-bit serialization 65 3.5 ? f s 0.5 ? f s 7 ? f s 2-lane 12-bit serialization 65 3 ? f s f s 6 ? f s 1-lane 16-bit serialization 62.5 8 ? f s f s 16 ? f s 1-lane 14-bit serialization 65 7 ? f s f s 14 ? f s 1-lane 12-bit serialization 65 6 ? f s f s 12 ? f s ltm 9008-14/ ltm 9007-14/ ltm 9006-14 26 90067814f applications information programmable lvds output current the default output driver current is 3.5ma. this current can be adjusted by control register a2 in the serial pro- gramming mode. available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4ma and 4.5ma. in the parallel programming mode, the sck pin can select either 3.5ma or 1.75ma. optional lvds driver internal termination in most cases, using just an external 100? termina- tion resistor will give excellent lvds signal integrity. in addition, an optional internal 100? termination resistor can be enabled by serially programming mode con - trol register a2. the internal termination helps absorb any reflections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. in the parallel programming mode the sdo pin enables internal termination. internal termination should only be used with 1.75ma, 2.1ma or 2.5ma lvds output current modes. d ata format table 2 shows the relationship between the analog input voltage and the digital data output bits. by default the output data format is offset binary . the 2s complement format can be selected by serially programming mode control register a1. digital output randomizer interference from the a/d digital outputs is sometimes unavoidable . digital interference may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can cause unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. the digital output is randomized by applying an exclusive- or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied an exclusive-or operation is applied between the lsb and all other bits. the fr and dco outputs are not affected. the output randomizer is enabled by serially programming mode control register a1. table 2. output codes vs input voltage a in + C a in C (2v range) d13-d0 (offset binary) d13-d0 (2s complement) >1.000000v +0.999878v +0.999756v 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 +0.000122v +0.000000v C0.000122v C0.000244v 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 C0.999878v C1.000000v ltm 9008-14/ ltm 9007-14/ ltm 9006-14 28 90067814f applications information table 4. serial programming mode register map ( par /ser = gnd) register a0: reset register (address 00h) d7 d6 d5 d4 d3 d2 d1 d0 reset x x x x x x x note that csa controls channels 1, 4, 5 and 8, csb controls channels 2, 3, 6 and 7. bit 7 reset software reset bit 0 = not used 1 = software reset. all mode control registers are reset to 00h. the adc is momentarily placed in sleep mode. after the reset spi write command is complete, bit d7 is automatically set back to zero. the reset register is write only. bits 6-0 unused, dont care bits. register a1 (csa): format and power-down register (address 01h with csa = gnd) d7 d6 d5 d4 d3 d2 d1 d0 dcsoff rand twoscomp sleep nap_8 nap_5 nap_4 nap_1 note that csa controls channels 1, 4, 5 and 8, csb controls channels 2, 3, 6 and 7. bit 7 dcsoff clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer on 1 = clock duty cycle stabilizer off. this is not recommended. bit 6 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = vdata output randomizer mode on bit 5 twoscomp tw o s complement mode control bit 0 = offset binary data format 1 = tw o s complement data format bits 4-0 sleep: nap_x sleep/nap mode control bits 00000 = normal operation 0xxx1 = channel 1 in nap mode 0xx1x = channel 4 in nap mode 0x1xx = channel 5 in nap mode 01xxx = channel 8 in nap mode 1xxxx = sleep mode. channels 1, 4, 5 and 8 are disabled note: any combination of channels can be placed in nap mode. serial programming mode to use the serial programming mode, par /ser should be tied to ground. the cs, sck, sdi and sdo pins become a serial interface that program the a / d mode control registers. data is written to a register with a 16-bit serial word. data can also be read back from a register to verify its contents. serial data transfer starts when cs is taken low. the data on the sdi pin is latched at the first 16 rising edges of sck. any sck rising edges after the first 16 are ignored. the data transfer ends when cs is taken high again. the first bit of the 16-bit input word is the r/w bit. the next seven bits are the address of the register (a6:a0). the final eight bits are the register data (d7:d0). if the r/w bit is low, the serial data (d7:d0) will be writ- ten to the register set by the address bits (a6:a0). if the r/w bit is high, data in the register set by the address bits (a6:a 0) will be read back on the sdo pin (see the timing diagrams section). during a read back command the register is not updated and data on sdi is ignored. the sdo pin is an open-drain output that pulls to ground with a 200? impedance. if register data is read back through sdo, an external 2k pull-up resistor is required. if serial data is only written and read back is not needed, then sdo can be left floating and no pull-up resistor is needed. table 4 shows a map of the mode control registers . 29 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 applications information register a1 (csb): format and power-down register (address 01h with csb = gnd) d7 d6 d5 d4 d3 d2 d1 d0 dcsoff rand twoscomp sleep nap_7 nap_6 nap_3 nap_2 note that csa controls channels 1, 4, 5 and 8, csb controls channels 2, 3, 6 and 7. bit 7 dcsoff clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer on 1 = clock duty cycle stabilizer off. this is not recommended. bit 6 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bit 5 twoscomp tw o s complement mode control bit 0 = offset binary data format 1 = tw o s complement data format bits 4-0 sleep: nap_4:nap_1 sleep/nap mode control bits 00000 = normal operation 0xxx1 = channel 2 in nap mode 0xx1x = channel 3 in nap mode 0x1xx = channel 6 in nap mode 01xxx = channel 7 in nap mode 1xxxx = sleep mode. channels 2, 3, 6 and 7 are disabled note: any combination of channels can be placed in nap mode. register a2: output mode register (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 ilvds 2 ilvds 1 ilvds 0 termon outoff outmode2 outmode1 outmode0 note that csa controls channels 1, 4, 5 and 8, csb controls channels 2, 3, 6 and 7. bits 7-5 ilvds 2: ilvds0 lvds output current bits 000 = 3.5ma lvds output driver current 001 = 4.0ma lvds output driver current 010 = 4.5ma lvds output driver current 011 = not used 100 = 3.0ma lvds output driver current 101 = 2.5ma lvds output driver current 110 = 2.1ma lvds output driver current 111 = 1.75ma lvds output driver current bit 4 termon lvds internal termination bit 0 = internal termination off 1 = internal termination on. lvds output driver current is 2x the current set by ilvds2: ilvds0. internal termination should only be used with 1.75ma, 2.1ma or 2.5ma lvds output current modes. bit 3 outoff output disable bit 0 = digital outputs are enabled. 1 = digital outputs are disabled. bits 2-0 outmode2:outmode0 digital output mode control bits 000 = 2-lanes, 16-bit serialization 001 = 2-lanes, 14-bit serialization 010 = 2-lanes, 12-bit serialization 011 = not used 100 = not used 101 = 1-lane, 14-bit serialization 110 = 1-lane, 12-bit serialization 111 = 1-lane, 16-bit serialization ltm 9008-14/ ltm 9007-14/ ltm 9006-14 30 90067814f applications information register a3: test pattern msb register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 outtest x tp13 tp12 tp11 tp10 tp9 tp8 note that csa controls channels 1, 4, 5 and 8, csb controls channels 2, 3, 6 and 7. bit 7 outtest digital output test pattern control bit 0 = digital output test pattern off 1 = digital output test pattern on bit 6 unused, dont care bit. bit 5-0 tp13:tp8 test pattern data bits (msb) tp13:tp8 set the test pattern for data bit 13 (msb) through data bit 8. register a4: test pattern lsb register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 note that csa controls channels 1, 4, 5 and 8, csb controls channels 2, 3, 6 and 7. bit 7-0 tp7:tp0 test pattern data bits (lsb) tp7:tp0 set the test pattern for data bit 7 through data bit 0 (lsb). software reset if serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. the first serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset, bit d7 in the reset register is written with a logic 1. after the reset spi write command is complete, bit d7 is automatically set back to zero. grounding and bypassing the ltm9008-14/ltm9007-14/ltm9006-14 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an internal ground plane in the first layer beneath the adc is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. bypass capacitors are integrated inside the package; ad- ditional capacitance is optional. the analog inputs, encode signals, and digital outputs should not be routed next to each other. ground fill and grounded vias should be used as barriers to isolate these signals from each other. the pin assignments of the ltm9008-14/ltm9007-14/ ltm9006-14 allow a flow- through layout that makes it possible to use multiple parts in a small area when a large number of adc channels are required . the device has similar layout rules to other bga pack - ages. the layout can be implemented with 6mil blind vias and 5mil traces. the pinout has been designed to minimize the space required to route the analog and digital traces. the analog and digital traces can essentially be routed within the width of the package. this allows multiple packages to be located close together for high channel count applications. trace lengths for the analog inputs and digital outputs should be matched as well as possible. 31 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 applications information heat transfer most of the heat generated by the ltm9008 -14/ ltm9007 -14/ ltm9006-14 is transferred from the die through the bot- tom of the package onto the printed circuit board. the ground pins should be connected to the internal ground planes by multiple vias. table 5. internal trace lengths pin name length (mm) pin name length (mm) pin name length (mm) pin name length (mm) e7 01a C 1.775 k8 05b C 0.379 e1 a in3 C 2.491 f10 dcob C 1.811 e8 01a + 1.947 k7 05b + 0.528 e2 a in3 + 2.505 f9 dcob + 1.812 c8 01b C 1.847 k9 06a C 1.866 g1 a in4 C 3.376 h7 fra C 1.117 d8 01b + 1.850 k10 06a + 1.865 g2 a in4 + 3.372 h8 fra + 1.038 b8 02 a C 3.233 l9 06b C 2.268 h2 a in5 C 3.301 j9 frb C 1.644 a8 02a + 3.246 l10 06b + 2.267 h1 a in5 + 3.346 j10 frb + 1.643 d7 02b C 0.179 m7 07a C 1.089 k2 a in6 C 2.506 a7 par /ser 3.838 c7 02b + 1.127 l7 07a + 0.179 k1 a in6 + 2.533 l6 sck 0.240 d10 03a C 2.126 p8 07b C 3.281 m2 a in7 C 3.198 e6 sdoa 0.453 d9 03a + 2.177 n8 07b + 3.149 m1 a in7 + 3.214 d6 sdob 0.274 e10 03b C 1.811 l8 08a C 1.862 n2 a in8 C 4.726 m6 sdi 1.069 e9 03b + 1.812 m8 08a + 1.847 n1 a in8 + 4.691 b3 v cm12 3.914 c9 04a C 3.199 m10 08b C 4.021 p6 clk C 4.106 f3 v cm34 0.123 c10 04a + 3.196 m9 08b + 4.016 p5 clk + 4.106 j3 v cm56 0.079 f7 04b C 0.706 b1 a in1 C 4.689 l5 csa 0.919 n3 v cm78 3.915 f8 04b + 0.639 b2 a in1 + 4.709 m5 csb 1.162 j8 05a C 0.392 c1 a in2 C 4.724 g8 dcoa C 1.157 j7 05a + 0.436 c2 a in2 + 4.769 g7 dcoa + 1.088 table 5 lists the trace lengths for the analog inputs and digital outputs inside the package from the die pad to the package pad. these should be added to the pcb trace lengths for best matching. the material used for the substrate is bt (bismaleimide- triazine), supplied by mitsubishi gas and chemical. in the dc to 125mhz range, the speed for the analog input signals is 198ps/in or 7.795ps/mm. the speed for the digital outputs is 188.5ps/in or 7.417ps/mm. ltm 9008-14/ ltm 9007-14/ ltm 9006-14 32 90067814f top side typical applications silkscreen top inner layer 2 inner layer 3 33 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 inner layer 5 typical applications inner layer 4 bottom side silkscreen bottom ltm 9008-14/ ltm 9007-14/ ltm 9006-14 34 90067814f typical application ltm9008-14 schematic e3 v + 3v to 6v clk + clk + gnd term sdob 3.3 aux jp6 1 2 3 r8 1k r11 10k en dis term sdoa 3.3 aux jp3 1 2 3 1 2 3 1 2 3 r3 1k en dis r5 31.6k 1% r13 31.6k 1% r4 10k lane csb jp3 1 2 3 r1 1k 1 lane 2 lane +1.8v +1.8v +1.8v +1.8v ilvds sck jp5 r7 1k 1.7ma 3.5ma lane csa jp2 r2 1k 1 lane 2 lane +1.8v par/ser par/ser par/ser sense vref sci sck csa csb sdoa sdob mosi jp4 r6 1k par ser r9 100 e1 ext ref r10 1k c1 2.2f, 0603 a1 a2 a3 a4 a5 a6 b4 b5 b7 c3 c4 c6 d1 d2 d5 e5 f1 f2 f4 f5 f6 g3 g4 g5 g6 h3 h4 h5 h6 j1 j2 j4 j5 j6 k5 k6 l1 l2 m3 m4 n4 n5 n6 n7 p1 p2 p3 p4 p7 a9 a10 b9 b10 h9 h10 n9 n10 p9 p10 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd a7 c5 b6 m6 l6 l5 m5 e6 d6 ltm9008-14 +1.8v r20 100 r14 (opt) l1 (opt) 1 2 3 5 4 r18 (opt) r25 (opt) c2 (opt) r24 (opt) c13 100f 10v r28 3k 90067814 ta02 out1a + out1a ? out1b + out1b ? out1a + out1a ? out1b + out1b ? e8 e7 d8 c8 out2a + out2a ? out2b + out2b ? out2a + out2a ? out2b + out2b ? a8 b8 c7 d7 out3a + out3a ? out3b + out3b ? out3a + out3a ? out3b + out3b ? d9 d10 e9 e10 out4a + out4a ? out4b + out4b ? out4a + out4a ? out4b + out4b ? c10 c9 f8 f7 out5a + out5a ? out5b + out5b ? out5a + out5a ? out5b + out5b ? j7 j8 k7 k8 out6a + out6a ? out6b + out6b ? out6a + out6a ? out6b + out6b ? k10 k9 l10 l9 ain1 + ain1 ? vcm12 ain1 + ain1 ? vcm12 b2 b1 b3 ain2 + ain2 ? ain2 + ain2 ? c2 c1 ain3 + ain3 ? vcm34 ain3 + ain3 ? vcm34 e2 e1 f3 vcm12 ain4 + ain4 ? ain4 + ain4 ? g2 g1 ain5 + ain5 ? vcm56 ain5 + ain5 ? vcm56 h2 h1 j3 ain6 + ain6 ? ain6 + ain6 ? k1 k2 ain8 + ain8 ? vcm78 ain8 + ain8 ? vcm78 n1 n2 n3 ain7 + ain7 ? ain7 + ain7 ? m1 m2 clk + clk ? clk + clk ? p5 p6 out7a + out7a ? out7b + out7b ? out7a + out7a ? out7b + out7b ? m8 l8 m9 m10 fra + fra ? frb + frb ? fra + fra ? frb + frb ? h8 h7 j10 j9 dcoa + dcoa ? dcob + dcob ? dcoa + dcoa ? dcob + dcob ? g7 g8 f9 f10 +1.8vo +1.8vo +1.8vo g9 g10 +1.8v +1.8v +1.8v +1.8v +1.8v +1.8v +1.8v +1.8v +1.8v d3 d4 e3 e4 k3 k4 l3 l4 c7 4.7pf c5 4.7pf r23 5.1 r37 100 r17 5.1 r22 49.9 1% r21 49.9 1% c9 0.01f r27 (opt) c6 0.01f (opt) c3 0.01f r26 (opt) r16 (opt) r15 (opt) j2 j1 e4 t1 maba- 007159-000000 fb1 blm31pg330sn1l fb2 blm31pg330sn1l c4 0.01f c8 0.01f r19 100 +1.8v +1.8vo lt3080edd c11 1f 0603 1 2 3 9 out out out out c56 0.1f c14 0.1f c10 4.7f 6.3v 0603 c12 1f 0603 4 set 6 nc 7 8 5 in in vctrl r29 180k 1% + +1.8v +1.8v c18 (opt) c23 (opt) c15 (opt) c19 (opt) c17 (opt) (same for other channels) r30 0 0603 r36 0 0603 r31 0 0805 r37 0 0805 r32 0 0603 r38 0 0603 in + in ? r48 100 35 90067814f ltm 9008-14/ ltm 9007-14/ ltm 9006-14 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view x aaa z 3 see notes bga 140 0709 rev a tray pin 1 bevel package in tray loading orientation component pin ?a1? ?b (140 places) d detail b package side view m x yzddd m zeee 0.4 ? 140x symbol a a1 a2 b b1 d e e d1 e1 aaa bbb ccc ddd eee min 2.57 0.35 2.22 0.45 0.35 nom 2.72 0.40 2.32 0.50 0.40 11.25 9.0 0.80 10.40 7.2 max 2.87 0.45 2.42 0.55 0.45 0.15 0.10 0.12 0.15 0.08 notes dimensions total number of balls: 140 y aaa z e e a2 d1 b e e1 ltmxxxxxx module detail a suggested pcb layout top view 3.600 2.800 2.000 1.200 0.400 0.000 0.400 1.200 2.000 2.800 3.600 5.200 4.400 4.400 5.200 3.600 2.800 2.000 1.200 0.400 0.000 0.400 1.200 2.000 2.800 3.600 4 pin ?a1? corner 1 p detail a c d e f g h j k l m n a b 10 9 8 7 6 5 4 3 2 pin 1 package bottom view b a z detail b substrate 0.27 ? 0.37 1.95 ? 2.05 // bbb z a1 b1 ccc z mold cap bga package 140-lead (11.25mm 9.00mm 2.72mm) (reference ltc dwg # 05-08-1849 rev a) please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. ltm 9008-14/ ltm 9007-14/ ltm 9006-14 36 90067814f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 1112 ? printed in usa related parts part number description comments adcs LTC2170-14/ltc2171-14/ ltc2172-14 14-bit, 25msps/40msps/65msps 1.8v quad adcs, ultralow power 178mw/234mw/360mw, 73.4db snr, 85db sfdr, serial lvds outputs, 7mm w 8mm qfn-52 ltc2173-14/ltc2174-14/ ltc2175-14 14-bit, 80msps/105msps/125msps 1.8v quad adcs, ultralow power 412mw/481mw/567mw, 73.4db snr, 85db sfdr, serial lvds outputs, 7mm w 8mm qfn-52 ltm9009-14/ltm9010-14/ ltm9011 -14 14-bit, 80msps/105msps/125msps 1.8v octal adcs, ultralow power 801mw/950mw/1145mw, 73.1db snr, 85db sfdr, serial lvds outputs, 11.25mm w 9mm bga-140 amplifiers/filters ltc6412 800mhz, 31db range, analog-controlled variable gain amplifier continuously adjustable gain control, 35dbm oip3 at 240mhz, 10db noise figure, 4mm w 4mm qfn-24 ltc6420-20 1.8ghz dual low noise, low distortion differential adc drivers for 300mhz if fixed gain 10v/v , 1nv/hz total input noise, 80ma supply current per amplifier, 3mm w 4mm qfn-20 ltc6421-20 1.3ghz dual low noise, low distortion differential adc drivers fixed gain 10v/v, 1nv/hz total input noise, 40ma supply current per amplifier, 3mm w 4mm qfn-20 ltc6605-7/ ltc6605-10/ ltc6605-14 dual matched 7mhz/10mhz/14mhz filters with adc drivers dual matched 2nd order lowpass filters with differential drivers, pin-programmable gain, 6mm w 3mm dfn-22 signal chain receivers ltm9002 14-bit dual channel if/baseband receiver subsystem integrated high speed adc, passive filters and fixed gain differential amplifiers typical application single-ended to differential conversion using ltc6409 and 50mhz lowpass filter (only one channel shown). filter for use at 61.44msps ltm9008-14 f3 f1 f2 c1 c2 b3 b1 b2 v cm12 a in2 + a in2 ? a in3 + a in3 ? v cm34 a in4 + a in4 ? a in8 + a in8 ? a in1 + a in1 ? o1a + o1a ? dco + dco ? fr + fr ? g2 g1 n1 n2 h7 h8 g8 g7 e7 e8 clk + clk ? p5 p6 b6 c5 1.8v 1.8v sense v dd v ref ov dd 33pf 100pf 150pf 180nh 180nh 3.3v 180nh 180nh 150pf 150 474 37.4 37.4 out ? out + v ocm in + v + in ? 474 75 75 66.9 66.9 0.1f 0.8pf 0.8pf 68pf 68pf 0.1f 90067814 ta03 ? ? ? ? + 150 shdn gnd 49.9 50 ? ? ? ltc6409 |
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